This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. When the DORD bit is written to zero, the MSB of the data word is transmitted first. When the DORD bit is written to one, the LSB of the data word is transmitted first. This bit must be set to enable any SPI operations. When the SPE bit is written to one, the SPI is enabled. This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set.
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